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本帖最后由 银杏大道南 于 2022-11-19 23:20 编辑
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F% w$ u0 O Z# S2 M2023芯片奥林匹克ISSCC放榜:& y( s- J7 @! ?' @* ?
清华+13、北大+6、电子科大+5、东南大学+3、复旦+3、浙大+3、等
0 [& v& P5 w* M' r- |7 Y(发新帖需审核,补充旧贴)5 `' d0 d% }. ^& O- {. b6 Z
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国内过去三年(2022-07-02)对JSSC贡献进入世界前100名高校情况如下:
, n" ?) H0 D* U* L$ z6 y; t4 E) T: c: K& L0 Q1. 清华大学,35篇,排名9
+ { U$ A) O: Y) A ?1 Z% y(澳门大学,31篇,并列12)
' u- k D! z- v6 g9 }7 I* K. C2. 电子科技大学,22篇,排名20
6 {) Y8 J& C( o4 N4 A# q# r& t(香港科技大学,19篇,排名24)
* v* G: J# a! J, w# m5 _3. 复旦大学,14篇,并列33$ J, g- X9 |) E! v9 d
4. 浙江大学/东南大学,均是13篇,并列38
) ~2 \) K) G; e2 }6. 中国科学院,11篇,并列45
" D4 t F/ ~7 v7 B I1 h7. 北京大学,8篇,并列56
+ I5 b: ^! W9 _) W; ?5 [/ S- g8. 西安电子科技大学,6篇,并列69
e$ q, n9 C5 q$ W(香港城市大学,4篇,并列94)
- r' D% U9 f% m* c9. 上海交通大学,4篇,并列945 T- `2 z S4 ~- x
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ISSCC2 b# \$ J" |4 l
2018年:复旦大学2篇、北京大学1篇、电子科大1篇;
: B# a( R: r% I5 ?/ V( T' k& _2019年:复旦大学有3篇,清华大学2篇,上海交大、东南大学分别有1篇;. J# M# X4 Z/ m3 k
2020年:清华大学5篇,电子科大3篇,北大、东南大学、西安交大、天津大学、复旦大学、上海交大各有1篇;& T' \- I( r% n- F
2021年:清华大学6篇,北大4篇,电子科大3篇,浙大2篇,东南大学、中科大各一篇
* x4 Y/ {* y) I+ [5 B" ]" _7 l- B合计排名:
6 t8 B* L v* j. y) x6 K' S1.清华。13篇* P- I: z3 y6 `% d
2.电子科大。7篇
3 I! @/ r' x0 g9 N) U3.北大\复旦。6篇
$ z" w l8 a! X3 |! B ?' x4.东南大学。3篇
, G: w6 m: W0 [9 ^0 x5.上海交大\浙大。2篇
2 m. n: a0 ? n, q+ {$ v6.西安交大\中科大\天津大学。1篇2 f8 ~: g5 Y5 _
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电子科大集成电路设计中青年师资统计
. x' f* f% p7 v2 u" n; ?1.康凯,杰青,1979年出生7 I* ~- L& P* |+ j4 F: [
研究方向为应用于5G通信和相控阵雷达的射频及毫米波集成电路。5 [4 H4 [) {9 D
[1]2010年9月,微电子与集成电路领域顶级国际期刊IEEE JOURNAL OF SOLID-STATE CIRCUITS(JSSC)上登载了电子科技大学电工学院康凯教授的论文《A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS》,这是电子科技大学首次以第一作者单位在JSSC上发表论文。
3 |9 j7 s5 D r! p5 M2 G7 Y[2]2017-10-13我校电子工程学院康凯教授团队在集成电路领域国际顶级期刊IEEE Journal of Solid-State Circuits上发表了题为“A 54.4-to-90 GHz Low-Noise Amplifier in 65 nm CMOS”(一款54.4~90 GHz的超宽带硅基低噪声放大器设计)的研究论文。电子工程学院康凯教授团队余益明博士为论文第一作者,其导师康凯教授为通讯作者,电子科技大学电子工程学院为唯一署名单位。这是我校博士生首次在该期刊上发表研究论文,且该工作全部在电子科技大学完成。2 m. w# d% h2 S. x/ Q# W/ \1 J2 X
[3]2013-11-28我校电工学院暨电磁研究所郭开喆同学(导师:康凯教授)的论文“A 60-GHz 21dBm Power Amplifier with a Fully Symmetrical 8-Way Transformer Power Combiner in 90nm CMOS”成功入选2014年国际固态电路会议ISSCC “学生科研前瞻”单元。
2 g. p8 S9 I- i F5 P* t; y( e[4]2018-04-13张净植的相关论文在业界顶尖的“国际固态电路会议(ISSCC)”上被发表,据了解,该论文是中国大陆地区发表在该会议上的首篇有关毫米波集成电路设计的论文,张净植提出的“基于强耦合变压器的电流提升技术”,可以“用一款芯片将全球多个频段全部覆盖,让‘全球通’变成可能。”。
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2.李qiang: y& A% _# U { Z1 }: P
主要研究方向为模拟与混合信号集成电路设计。
+ _/ u) X" B! E) }( s: R[1]Pengfei Zhai, Zheng Zhu, Xiong Zhou, Yan Cai, Fan Zhang, Qiang Li, "An on-chip power-supply noise analyzer with compressed sensing and enhanced quantization," IEEE Journal of Solid-State Circuits (JSSC), Jan. 2022.+ [" \" T' k' `) v! ?$ P9 @
[2]Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li, “A 130-dB CMRR instrumentation amplifier with common-mode replication,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2022.
+ Z& ^; l6 ?+ B+ A3 f[3]Xin Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Y.-L. Chung, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Qiang Li, Meng-Fan Chang, “A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips,” IEEE Journal of Solid-State Circuits (JSSC), Sep. 2021.5 x; \) {$ I2 s
[4]Ruiqi Guo, Zhiheng Yue, Xin Si, T. Hu, H. Li, L. Tang, Y. Wang, L. Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin, “A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2021.
9 p5 L ?8 m3 o1 B/ k[5]Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li, “An AC-coupled instrumentation amplifier achieving 110-dB CMRR at 50 Hz with chopped pseudoresistors and successive-approximation based capacitor trimming,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2021. [* y# H. Q1 e. q
[6]Zheng Zhu, Xiong Zhou, Yuheng Du, Yao Feng, Qiang Li, "A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration," IEEE Journal of Solid-State Circuits (JSSC), Jun. 2020.
: c, A+ A' J% ][7]Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li, “A 130dB CMRR instrumentation amplifier with common-mode replication,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020.
5 Y0 Z5 i, Z0 B[8]Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li, “A scalable 20GHz on-die power supply noise analyzer with compressed sensing,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020. (ISSCC STGA Award)0 c; t0 h9 k# w' q
[9]Xin Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Z. Zhang, S.-H. Sie, W.-C. Wei, Y.-C. Lo, T.-H. Wen, T.-H. Hsu, Y.-K. Chen, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Qiang Li, Meng-Fan Chang, “A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020.
) M+ D) v8 A( x1 ?[10]Xin Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, Meng-Fan Chang, “A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2020.
" T' C! R. p$ r9 s2 A[11]Lishan Lv, Xiong Zhou, Zhiliang Qiao, Qiang Li, "Inverter-based subthreshold amplifier techniques and their application in 0.3V ΔƩ-modulators," IEEE Journal of Solid-State Circuits (JSSC), May 2019.4 z5 d& o$ ]0 Q/ C8 b
[12]Zhaoming Ding, Xiong Zhou, Qiang Li, "A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2019. (VLSI invited submission)
1 E; I' D' i, R$ z& c+ ^1 R9 r& P[13]Xin Si, Jia-Jing Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, Meng-Fan Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN based machine learning,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019.
7 z* ?9 N, G! L. p[14]Lishan Lv, Ankesh Jain, Xiong Zhou, Joachim Becker, Qiang Li, Maurits Ortmanns, "A 0.4V Gm-C proportional-integrator-based continuous-time ΔƩ modulator with 50kHz BW and 74.4dB SNDR," IEEE Journal of Solid-State Circuits (JSSC), Nov. 2018., P7 ]' ^% r* [4 n1 \! A
[15]Xiaofei Ma, Yan Lu, R. Martins, Qiang Li, "A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS," International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. (ISSCC STGA Award)8 Z, {" z* Y( k* g
[16]W.-S. Khwa, J.-J. Chen, J.-F. Li, Xin Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y. Chen, Qiang Li, S. Yu, Meng-Fan Chang, “A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018.8 @3 C9 ]& j$ G
# M- X' J# }* j3.罗讯 . I7 B ?. H9 \1 v
本科电子科大,直博电子科大
: I4 E* _9 x9 @* k[1]B. Yang, H. Qian, T. Wang, and X. Luo, “A CMOS wideband watt-level 4096-QAM digital power amplifier using reconfigurable power combining transformer,” IEEE J. Solid-State Circuits (JSSC), early access, 2022.$ i2 y* }0 X3 A
[2]Z. Deng, H. Qian, and X. Luo, “A reflectionless receiver with absorptive IF amplifier and dual-path noise-cancelling LNA,” IEEE J. Solid-State Circuits (JSSC), vol. 37, no. 8, pp. 2309–2319, Aug. 2022.
8 I( X4 C+ R; H3 H1 A[3]Y. Shu, H. Qian, X. Gao, and X. Luo, “A low phase noise and high FoM distributed-swing-boosting multi-core oscillator using harmonic-impedance-expanding technique,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 12, pp. 3728–3739, Dec. 2021.
" H% Z; T9 d, c) d[4]B. Yang, H. Qian, and X. Luo, “Quadrature switched/floated capacitor power amplifier with reconfigurable self-coupling canceling transformer for deep back-off efficiency enhancement,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 12, pp. 3715–3727, Dec. 2021.; z, b+ d1 H3 q$ u0 [" l0 m3 ~
[5]H. Qian, J. Zhou, B. Yang, and X. Luo, “A 4-element digital modulated polar phased-array transmitter with phase modulation phase-shifting,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3331–3347, Nov. 2021.% F# d5 f5 Y3 p$ k& ? M
[6]Z. Deng, J. Zhou, H. Qian, and X. Luo, “A 22.9-38.2-GHz dual-path noise-canceling LNA with 2.65-4.62-dB NF in 28-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 11, pp. 3348–3359, Nov. 2021. (IEEE JSSC Popular Ranking No.4, Nov. 2021)7 |6 {# m: k! ~* f
[7]Y. Shu, H. Qian, and X. Luo, “A 2-D mode-switching quad-core oscillator using E-M mixed-coupling resonance boosting,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 6, pp. 1711–1721, Jun. 2021.
1 Z# o# ]6 {' r% H[8]H. Qian, B. Yang, J. Zhou, H. Xu, and X. Luo, “A quadrature digital power amplifier with hybrid Doherty and impedance boosting for complex domain power back-off efficiency enhancement,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 5, pp. 1487–1501, May 2021. (IEEE JSSC Popular Ranking No.10, May 2021)
0 Q5 ~- _1 W3 j' H2 d[9]H. Qian, Y. Shu, J. Zhou, and X. Luo, “A 20–32-GHz quadrature digital transmitter using synthesized impedance variation compensation,” IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 5, pp. 1297–1309, May 2020.
$ g- ~) ?, _8 l( r1 o1 w[10]B. Yang, H. Qian, and X. Luo, “A watt-level quadraqure switched/floated-capacitor power amplifer with back-off efficiency enhancement in complex domain using reconfigurable self-coupling cancelling transformer,” in IEEE ISSCC, Virtual, Feb. 2021.
( K/ W \5 N: y; w" W8 d0 @[11]Y. Shu, H. Qian, X. Gao, and X. Luo, “A 3.09-to-4.04GHz distributed-boosting and harmonic-impedance-expanding multi-core oscillator with -138.9dBc/Hz at 1MHz offset and 195.1dBc/Hz FoM,” in IEEE ISSCC, Virtual, Feb. 2021. (ISSCC2021 RF Session Highlight)
4 y g3 U6 M7 K! n4 j[12]Y. Shu, H. Qian, and X. Luo, “A 18.6-to-40.1GHz 201.7dBc/Hz FoMT multi-core oscillator using E-M mixed-coupling resonance boosting,” in IEEE ISSCC, San Franscisco, CA, USA, Feb. 2020./ o1 @5 v- } ~$ _% D% J1 ^ O5 M' w
1 d% K1 x" A v4.刘佳欣0 A, y3 M# X4 c' j% W4 s% f
本科毕业于山东大学,硕博毕业于电子科技大学,美国德州大学奥斯汀分校联合培养博士生,清华大学博士后。
) t. S4 ?% X/ n9 j D8 {3 b主要研究方向为模拟与混合信号集成电路设计,尤其是模数转换器(ADC)芯片的设计。3 A2 q' H6 L9 Z, Y4 H: i
代表性论文/ S/ K6 o0 _" m) [% p0 |
[1]Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang and Nan Sun, “A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4x Passive Gain and Second-Order DAC Mismatch Error Shaping”, IEEE Journal of Solid-State Circuits (JSSC), 2021.
5 Q# c3 Y7 H: O2 b5 w[2]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13-bit 0.005mm^2 40-MS/s SAR ADC with kT/C Noise Cancellation”, IEEE Journal of Solid-State Circuits (JSSC), 2020. (ISSCC invited submission)" V+ w6 V/ o" A5 Z: e; s
[3]Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, and Nan Sun, “A 0.029-mm^2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
, \ N( k `0 B) b9 w8 ?8 x[4]Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun, “A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering,” IEEE International Solid-State Circuits Conference (ISSCC), 2021.0 @) E; b1 }+ H
[5]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13b 0.005mm^2 40MS/s SAR ADC with kT/C Noise Cancellation”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
6 V8 Q# p9 `1 N# ]0 S[6]Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, and Nan Sun, “A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-order Mismatch Error Shaping,” IEEE International Solid-State Circuits Conference (ISSCC). 2020.
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5.周军) Y* }% ]" `! m7 ?0 o, i2 M: Z
本科电子科大,博士英国纽斯卡尔大学
, h& T! {5 M# m: V在芯片领域奥林匹克会议ISSCC 2021上,信息与通信工程学院周军教授团队宣读了团队在人工智能芯片领域的最新工作BioAIP:A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring。该论文是电子科技大学在人工智能芯片领域的第一篇ISSCC顶会论文。电子科技大学为该论文唯一单位,周军教授指导的博士生刘嘉豪为第一作者,周军教授为通讯作者,芯片设计团队共包含12位成员,芯片的前后端设计工作均在团队内完成。
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6.王政5 {/ Q/ T6 J- ~4 M; P! t
清华本硕,加州大学欧文分校博士
' _4 E/ r0 R2 ?/ A' s% ]电子科学与工程学院王政教授团队在具有“芯片奥林匹克”之称的IEEE国际固态电路会议(ISSCC 2022)上发表了其团队在高性能锁相环频率综合器领域的突破性研究成果A 25.8GHz Integer-N PLL with Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance。该项技术打破了传统电荷泵设计中噪声-功耗的折衷关系,将电荷泵锁相环的性能优值(Figure-of-merit, FoM)推进到了-250dB以下(-252.8dB)。电子科技大学为该论文唯一单位,王政教授指导的博士生耿新林为第一作者,王政教授为通讯作者。6 ^3 e `& N( _$ {' b0 d
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7.唐鹤
T" ?) }. y L( d8 B电子科大本, 硕士,伊州理工大学。 博士,加州大学河滨分校。, t- ]" O4 c r7 ~! N
我校电子科学与工程学院唐鹤教授团队在《IEEE Journal of Solid-State Circuits》(JSSC)上发表了题为“A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting”的研究论文。唐鹤教授团队的庄浩宇老师为论文第一作者,电子科学与工程学院为第一单位,合作方为美国德州大学奥斯汀分校的孙楠教授。
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8.王成,+ Q/ B3 o1 c4 T+ ]5 w8 ~: V: a$ \6 M
2008年本科毕业于清华大学工程物理系,2011年硕士毕业于中国工程物理研究院研究生部,2020年博士毕业于美国麻省理工学院电气工程与计算机科学系(EECS)。2011年~2015年,担任中国工程物理研究院电子工程研究所助理研究员。2019年-2021年,担任美国亚德诺半导体研究科学家。2021年2月,加入电子科技大学电子科学与工程学院(示范性微电子学院)。
0 s3 L* j* X' t2 G2 }所提出的芯片级分子时钟作为封面文章发表于2018年7月的Nature子刊Nature Electronics,并被MIT新闻等媒体报道。在有着集成电路领域国际奥林匹克之称的国际固态电路会议(ISSCC)上发表3篇论文,在领域旗舰刊物IEEE固态电路杂志(JSSC)发表6篇论文。
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9.文光俊
5 S, {" P9 J E4 s3 R- U4 _我校信息与通信工程学院文光俊教授团队与美国德州大学奥斯汀分校孙楠教授团队合作,在集成电路领域国际旗舰期刊IEEE Journal of Solid-State Circuits上发表了题为“A 0.029-mm² 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer”(一款基于单OTA和二阶噪声整形SAR量化器的0.029mm²每步转换能耗17飞焦耳的三阶连续时间ΔΣ模数转换器)的研究论文。文光俊教授指导的博士研究生刘佳欣为论文第一作者,电子科技大学信息与通信工程学院为第一作者单位。据悉,这是文光俊教授团队第二次在该期刊上发表研究论文。# P4 W7 m7 @# S6 S% G* D; [
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