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发表于 2025-2-28 11:50:21
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北京大学集成电路学院/集成电路高精尖创新中心在人工智能和数字加速方面发表论文4篇,内容包括:
(1)可满足性求解器(论文题目:SKADI: A 28nm Complete K-SAT Solver Featuring Dual-path SRAM-based Macro and Incremental Update with 100% Solvability,博士生吴子涵为第一作者,通讯作者为唐希源、王源);
(2)基于存算一体的多内容生成扩散模型加速器芯片(论文题目:A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Efficient Multi-Task Content Generation,博士生景亦奇为第一作者,通讯作者为贾天宇、叶乐);
(3)超低功耗语音活动检测检测芯片(论文题目:A 0.22mm2161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction,博士生刘影、李杰和硕士生张麒宁为共同第一作者,通讯作者为沈林晓、王志轩);
(4)Nebula——用于三维点云分析的高能效神经网络加速器(论文题目:A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation,北京大学深圳研究生院信息工程学院博士周长春为第一作者,通讯作者为杨玉超、焦海龙,是北京大学深圳研究生院首次在ISSCC发表论文)
在图像芯片方面发表了论文1篇,内容包括:
(1)采用光电流自驱动的像素级电流相位型ADC的红外焦平面成像芯片(论文题目:A 320×256 6.9mW 2.2mK-NETD 120.4dB-DR LW - IRFPA with Pixel-Paralleled Light-Driven 20b Current-to-Phase ADC,博士生卓毅为第一作者,通讯作者为张雅聪、鲁文高)
在有线通信方面发表论文4篇,内容包括:
(1)突发模式快速响应接收机芯片(论文题目:A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON,博士生张泊洋、叶天辰为共同第一作者,通讯作者为盖伟新);
(2)高密度无源信道信号完整性测试芯片(论文题目:A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS,博士生吴广栋、李元梁和博士毕业生叶秉奕为共同第一作者,通讯作者为盖伟新);
(3)224Gb/s极短距接收机芯片(论文题目:A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS,博士毕业生叶秉奕为第一作者,通讯作者为盖伟新);
(4)面向芯粒集成的全双工收发机芯片(论文题目:A 64Gb/s/wire 10.5Tb/s/mm/layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS,博士生王知非为第一作者,通讯作者为盖伟新)
在模拟与混合信号集成电路方面发表论文6篇,内容包括:
(1)采用增益嵌入式自举采样器的高能效ΔΣ模数转换器芯片(论文题目:A 12.2uW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler,博士生栾耀晖为第一作者,通讯作者为沈林晓);
(2)高精度高能效免校准流水线-逐次逼近型模数转换器芯片(论文题目:A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch Error Shaping Technique and Negative-R-Assisted Residue Integrator,博士生高继航为第一作者,通讯作者为沈林晓,该论文遴选为2025 ISSCC Data Converter方向亮点论文);
(3)高精度低延迟模数转换器芯片(论文题目:A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique,博士生王宗楠为第一作者,通讯作者为唐希源);
(4)高能效轨到轨高线性度噪声整形逐次逼近模数转换器系统芯片(论文题目:A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting,博士生叶思源为第一作者,通讯作者为沈林晓);
(5)易驱动的轨到轨高能效流水线-逐次逼近型模数转换器芯片(论文题目:An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input Buffer Sampling Scheme and Fast-Robust Background Inter-Stage Gain Calibration,博士生陈卓毅为第一作者,通讯作者为沈林晓);
(6)高精度电容读出芯片(论文题目:A 185.2dB-FoMs 8.7-aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Techniquess,博士生李秉芮为第一作者,通讯作者为唐希源)。 |
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